The present invention relates to a chip layout most suitable for logic LSI circuits such as microprocessors.
Generally speaking, advancement in fine pattern technology for manufacturing semiconductor LSI circuits has enabled high density packing. Also, designs for chip layout have been introduced in order to make signal line routing as short as possible for high speed operation. An example of prior art technology based on the above technical concept can be found in the layout method for MOS-LSI microprocessors proposed in U.S. Pat. No. 3,987,418, as shown in FIG. 1. In the figure, each rectangular frame (112 to 152) represents a circuit block having a unitary function. Each block is laid out in a high density packing along a signal flow represented by arrows. This prior art method, however, is accompanied with a drawback that if an additional circuit function is required for the microprocessor to improve its performance, a complete change in layout is needed because of the lack of any space in the layout area. As an example, a microprocessor circuit designed by the present inventor is shown in FIG. 2, which circuit includes the functions of the prior art microprocessor shown in FIG. 1. This microprocessor circuit shown in FIG. 2 has three additional circuits not included in the microprocessor of FIG. 1, i.e., O-C 206 (Operand-Cache), I-C 207 Instruction-Cache) and micro-ROM 211 (Microprogram ROM}. These additional circuits are used for improving the operation speed of the microprocessor.
With the layout method shown in FIG. 1, the additional circuits 206, 207 and 211 of FIG. 2 cannot be introduced unless a complete change in layout is performed, because no space in the layout area is left.